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NJU6682 160-common x 132-segment 4-level gray scale bitmap lcd driver general description package outline the NJU6682 is a 160-common x 132-segment 4-level gray scale bit map lcd driver to display graphics or characters. it contains 84,480-bit display data ram, microprocessor interface circuits, instruction decoder, and common and segment drivers. an image data from cpu through the serial or 8-bit/16-bit parallel interface are stored into the 84,480 bits internal display data ram and are displayed on the lcd panel through the commons and segments drivers. the NJU6682 features 4-level gray scale display function creating 4 types of gray scale (white / light gray / dark gray / black) and black & white display function. the NJU6682 contains a built-in osc circuit for reducing external components. and it features partial display function containing selectable active display block(s) (two blocks max.) and optimizing the duty cycle ratio. this function dramatically reduces the operating current, setting the optimum boosted voltage combined with a programmable voltage booster circuit and an electrical variable resister. as result, it reduces the operating current. the operating voltage from 2.4v to 3.3v and low operating current are suitable for small size battery operation items. features direct correspondence of display data ram to lcd pixel display method ? 4 level gray scale / black & white display data ram ? 84,480 bits ;( 160-com x 132-seg) x 2 (double of the display size) x 2bit lcd drivers ? 160-common and 132-segment direct connection to 8-bit / 16-bit microprocessor interface for both of 68 and 80 type mpu serial interface (si, scl, a0, cs) partial display function (two limited active display blocks setting. duty ratio set automatically.) variable ram mapping ? the display screen can be composed from the ram area in a maximum of 8 blocks discontinuity. easy vertical scroll by setting the start line address of over size display data ram (this function doesn?t work in variable ram mapping mode ) programmable bias ratio selection ; 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14 bias common driver order assignment by mask option version c 0 to c 159 (pin name) NJU6682a com 0 to com 159 NJU6682b com 159 to com 0 useful instruction sets display on/off, display start line-address set, column-address set, row-address set, status read, display data read/write, normal or reverse display, whole display/normal display, partial display, n-line inverse set, evr resister set, variable ram mapping mode, gray scale level select, bias select, booster select (7-times maximum), read modify write, reset, power supply selection, driver outputs on/off, power save, adc select, display mode select, 8-bit / 16-bit buss select. power supply circuit for lcd; programmable booster circuits (7 times maximum, voltage boosting polarity : negative voltage (v dd common), voltage adjust circuit, voltage follower (x 4)) precision electrical variable resistance (201 step) low operating current t.b.d ( typ. ) operating voltage 2.4 to 3.3 v lcd driving voltage 6.0 to 18.0v package outline bumped chip / cof c-mos technology ( substrate : n ) NJU6682cj preliminary
NJU6682 pad location chip center :x=0um,y=0um chip size :x=8.27m,y=5.67mm chip thickness :675um +/- 30um bump size :45um x 83um pad pitch :60um (min) bump height :17.5um (typ) bump material :au voltage boosting polarity : negative voltage (v dd common) substrate : n c 79 c 78 s 79 s 78 c 81 c 80 x y c 159 c 158 s 130 s 131 s 80 s 81 c 1 c 0 s 1 s 0 osc 1 v 4 res ps 0 rd c4 - d 6 (scl) d 1 a0 c6 - d 5 v 5 cs v out c2 - c1 + v ss d 7 (si) wr d 2 c2 + v dd vr v dd sel68 d 0 v ss d 4 d 3 c5 - c3 - v 3 v 1 c1 - v 2 osc 2 d 13 d 8 d 12 d 14 d 9 d 11 d 10 d 15 ps 1 dummy0 dummy1 dummy2 v dd
NJU6682 pad coordinates chip size 8.27 5.67mm(chip center x=0 m, y=0 m) pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 1 v dd -3933 -2675 51 c 1 3975 -2126 2 dummy0 -3863 -2675 52 c 2 3975 -2066 3 dummy1 -3793 -2675 53 c 3 3975 -2006 4 dummy2 -3723 -2675 54 c 4 3975 -1946 5 ps 1 -3562 -2675 55 c 5 3975 -1886 6 ps 0 -3325 -2675 56 c 6 3975 -1826 7 sel68 -3105 -2675 57 c 7 3975 -1766 8 res -2869 -2675 58 c 8 3975 -1706 9 v ss -2712 -2675 59 c 9 3975 -1646 10 osc 1 -2555 -2675 60 c 10 3975 -1586 11 osc 2 -2319 -2675 61 c 11 3975 -1526 12 cs -2098 -2675 62 c 12 3975 -1466 13 a0 -1862 -2675 63 c 13 3975 -1406 14 wr -1641 -2675 64 c 14 3975 -1346 15 rd -1405 -2675 65 c 15 3975 -1286 16 d 0 -1168 -2675 66 c 16 3975 -1226 17 d 1 -948 -2675 67 c 17 3975 -1166 18 d 2 -727 -2675 68 c 18 3975 -1106 19 d 3 -507 -2675 69 c 19 3975 -1046 20 d 4 -287 -2675 70 c 20 3975 -986 21 d 5 -66 -2675 71 c 21 3975 -926 22 d 6 (scl) 153 -2675 72 c 22 3975 -866 23 d 7 (si) 374 -2675 73 c 23 3975 -806 24 d 8 594 -2675 74 c 24 3975 -746 25 d 9 814 -2675 75 c 25 3975 -686 26 d 10 1035 -2675 76 c 26 3975 -626 27 d 11 1255 -2675 77 c 27 3975 -566 28 d 12 1476 -2675 78 c 28 3975 -506 29 d 13 1696 -2675 79 c 29 3975 -446 30 d 14 1916 -2675 80 c 30 3975 -386 31 d 15 2137 -2675 81 c 31 3975 -326 32 v ss 2298 -2675 82 c 32 3975 -266 33 v out 2368 -2675 83 c 33 3975 -206 34 c6 - 2464 -2675 84 c 34 3975 -146 35 c5 - 2613 -2675 85 c 35 3975 -86 36 c4 - 2683 -2675 86 c 36 3975 -26 37 c3 - 2832 -2675 87 c 37 3975 34 38 c2 - 2902 -2675 88 c 38 3975 94 39 c2 + 3050 -2675 89 c 39 3975 154 40 c1 - 3120 -2675 90 c 40 3975 214 41 c1 + 3269 -2675 91 c 41 3975 274 42 v dd 3339 -2675 92 c 42 3975 334 43 vr 3519 -2675 93 c 43 3975 394 44 v 5 3589 -2675 94 c 44 3975 454 45 v 4 3659 -2675 95 c 45 3975 514 46 v 3 3729 -2675 96 c 46 3975 574 47 v 2 3799 -2675 97 c 47 3975 634 48 v 1 3869 -2675 98 c 48 3975 694 49 v dd 3939 -2675 99 c 49 3975 754 50 c 0 3975 -2186 100 c 50 3975 814
NJU6682 pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 101 c 51 3975 874 151 c 101 2670 2675 102 c 52 3975 934 152 c 102 2610 2675 103 c 53 3975 994 153 c 103 2550 2675 104 c 54 3975 1054 154 c 104 2490 2675 105 c 55 3975 1114 155 c 105 2430 2675 106 c 56 3975 1174 156 c 106 2370 2675 107 c 57 3975 1234 157 c 107 2310 2675 108 c 58 3975 1294 158 c 108 2250 2675 109 c 59 3975 1354 159 c 109 2190 2675 110 c 60 3975 1414 160 c 110 2130 2675 111 c 61 3975 1474 161 c 111 2070 2675 112 c 62 3975 1534 162 c 112 2010 2675 113 c 63 3975 1594 163 c 113 1950 2675 114 c 64 3975 1654 164 c 114 1890 2675 115 c 65 3975 1714 165 c 115 1830 2675 116 c 66 3975 1774 166 c 116 1770 2675 117 c 67 3975 1834 167 c 117 1710 2675 118 c 68 3975 1894 168 c 118 1650 2675 119 c 69 3975 1954 169 c 119 1590 2675 120 c 70 3975 2014 170 c 120 1530 2675 121 c 71 3975 2074 171 c 121 1470 2675 122 c 72 3975 2134 172 c 122 1410 2675 123 c 73 3975 2194 173 c 123 1350 2675 124 c 74 3975 2254 174 c 124 1290 2675 125 c 75 3975 2314 175 c 125 1230 2675 126 c 76 3975 2374 176 c 126 1170 2675 127 c 77 3975 2434 177 c 127 1110 2675 128 c 78 3975 2494 178 c 128 1050 2675 129 c 79 3975 2554 179 c 129 990 2675 130 c 80 3930 2675 180 c 130 930 2675 131 c 81 3870 2675 181 c 131 870 2675 132 c 82 3810 2675 182 c 132 810 2675 133 c 83 3750 2675 183 c 133 750 2675 134 c 84 3690 2675 184 c 134 690 2675 135 c 85 3630 2675 185 c 135 630 2675 136 c 86 3570 2675 186 c 136 570 2675 137 c 87 3510 2675 187 c 137 510 2675 138 c 88 3450 2675 188 c 138 450 2675 139 c 89 3390 2675 189 c 139 390 2675 140 c 90 3330 2675 190 c 140 330 2675 141 c 91 3270 2675 191 c 141 270 2675 142 c 92 3210 2675 192 c 142 210 2675 143 c 93 3150 2675 193 c 143 150 2675 144 c 94 3090 2675 194 c 144 90 2675 145 c 95 3030 2675 195 c 145 30 2675 146 c 96 2970 2675 196 c 146 -30 2675 147 c 97 2910 2675 197 c 147 -90 2675 148 c 98 2850 2675 198 c 148 -150 2675 149 c 99 2790 2675 199 c 149 -210 2675 150 c 100 2730 2675 200 c 150 -270 2675
NJU6682 pad no. terminal x(um) y(um) pad no. terminal x(um) y(um) 201 c 151 -330 2675 251 s 90 -3330 2675 202 c 152 -390 2675 252 s 89 -3390 2675 203 c 153 -450 2675 253 s 88 -3450 2675 204 c 154 -510 2675 254 s 87 -3510 2675 205 c 155 -570 2675 255 s 86 -3570 2675 206 c 156 -630 2675 256 s 85 -3630 2675 207 c 157 -690 2675 257 s 84 -3690 2675 208 c 158 -750 2675 258 s 83 -3750 2675 209 c 159 -810 2675 259 s 82 -3810 2675 210 s 131 -870 2675 260 s 81 -3870 2675 211 s 130 -930 2675 261 s 80 -3930 2675 212 s 129 -990 2675 262 s 79 -3975 2517 213 s 128 -1050 2675 263 s 78 -3975 2457 214 s 127 -1110 2675 264 s 77 -3975 2397 215 s 126 -1170 2675 265 s 76 -3975 2337 216 s 125 -1230 2675 266 s 75 -3975 2277 217 s 124 -1290 2675 267 s 74 -3975 2217 218 s 123 -1350 2675 268 s 73 -3975 2157 219 s 122 -1410 2675 269 s 72 -3975 2097 220 s 121 -1470 2675 270 s 71 -3975 2037 221 s 120 -1530 2675 271 s 70 -3975 1977 222 s 119 -1590 2675 272 s 69 -3975 1917 223 s 118 -1650 2675 273 s 68 -3975 1857 224 s 117 -1710 2675 274 s 67 -3975 1797 225 s 116 -1770 2675 275 s 66 -3975 1737 226 s 115 -1830 2675 276 s 65 -3975 1677 227 s 114 -1890 2675 277 s 64 -3975 1617 228 s 113 -1950 2675 278 s 63 -3975 1557 229 s 112 -2010 2675 279 s 62 -3975 1497 230 s 111 -2070 2675 280 s 61 -3975 1437 231 s 110 -2130 2675 281 s 60 -3975 1377 232 s 109 -2190 2675 282 s 59 -3975 1317 233 s 108 -2250 2675 283 s 58 -3975 1257 234 s 107 -2310 2675 284 s 57 -3975 1197 235 s 106 -2370 2675 285 s 56 -3975 1137 236 s 105 -2430 2675 286 s 55 -3975 1077 237 s 104 -2490 2675 287 s 54 -3975 1017 238 s 103 -2550 2675 288 s 53 -3975 957 239 s 102 -2610 2675 289 s 52 -3975 897 240 s 101 -2670 2675 290 s 51 -3975 837 241 s 100 -2730 2675 291 s 50 -3975 777 242 s 99 -2790 2675 292 s 49 -3975 717 243 s 98 -2850 2675 293 s 48 -3975 657 244 s 97 -2910 2675 294 s 47 -3975 597 245 s 96 -2970 2675 295 s 46 -3975 537 246 s 95 -3030 2675 296 s 45 -3975 477 247 s 94 -3090 2675 297 s 44 -3975 417 248 s 93 -3150 2675 298 s 43 -3975 357 249 s 92 -3210 2675 299 s 42 -3975 297 250 s 91 -3270 2675 300 s 41 -3975 237
NJU6682 pad no. terminal x(um) y(um) 301 s 40 -3975 177 302 s 39 -3975 117 303 s 38 -3975 57 304 s 37 -3975 -2 305 s 36 -3975 -62 306 s 35 -3975 -122 307 s 34 -3975 -182 308 s 33 -3975 -242 309 s 32 -3975 -302 310 s 31 -3975 -362 311 s 30 -3975 -422 312 s 29 -3975 -482 313 s 28 -3975 -542 314 s 27 -3975 -602 315 s 26 -3975 -662 316 s 25 -3975 -722 317 s 24 -3975 -782 318 s 23 -3975 -842 319 s 22 -3975 -902 320 s 21 -3975 -962 321 s 20 -3975 -1022 322 s 19 -3975 -1082 323 s 18 -3975 -1142 324 s 17 -3975 -1202 325 s 16 -3975 -1262 326 s 15 -3975 -1322 327 s 14 -3975 -1382 328 s 13 -3975 -1442 329 s 12 -3975 -1502 330 s 11 -3975 -1562 331 s 10 -3975 -1622 332 s 9 -3975 -1682 333 s 8 -3975 -1742 334 s 7 -3975 -1802 335 s 6 -3975 -1862 336 s 5 -3975 -1922 337 s 4 -3975 -1982 338 s 3 -3975 -2042 339 s 2 -3975 -2102 340 s 1 -3975 -2162 341 s 0 -3975 -2222
NJU6682 block diagram output assignment register internal bus com driver shift register seg driver display data latch display data ram 132 x 2 x 160 x 2 row address decoder line address decoder column address decoder line counter column address counter 6bit column address register 6bit multiplex row address register vss v dd 5 v 1 to v 5 common timing generator display timing generator osc osc 2 i/o buffer status bf bus holder instruction decoder reset res mpu interface sel68 ps 0 a0 cs wr rd d 0 to d 5 d 6 (scl) d 7 (si) osc 1 start line registe r gray scale/black & white control 132 frc/pwm controller d 8 tod 15 voltage generator c 1 + c 1 - c 2 + c 2 - c 3 - c 4 - vr c 5 - c 6 - 132 x 2 i/o buffer c 0 c 159 s 131 s 0 ps 1
NJU6682 terminal description no. symbol i/o function 2 ? 4 dummy 0 ? dummy 2 dummy terminals these are open terminals electrically. 1,42,49 v dd power power supply terminal (+2.4v ? +3.3v) 9,32 v ss gnd ground terminal (0v) lcd driving voltage supplying terminals. in case of the external power supply operation without internal power supply operation, each level of lcd driving voltage is supplied from outside fitting with following relation. v dd v 1 v 2 v 3 v 4 v 5 v out in case of the internal power supply, lcd driving voltages v 1 -v 4 depending on the bias selection are supplied as shown in follows; bias v 1 v 2 v 3 v 4 1/4bias v 5 +3/4v lcd v 5 +2/4v lcd v 5 +2/4v lcd v 5 +1/4v lcd 1/5bias v 5 +4/5v lcd v 5 +3/5v lcd v 5 +2/5v lcd v 5 +1/5v lcd 1/6bias v 5 +5/6v lcd v 5 +4/6v lcd v 5 +2/6v lcd v 5 +1/6v lcd 1/7bias v 5 +6/7v lcd v 5 +5/7v lcd v 5 +2/7v lcd v 5 +1/7v lcd 1/8bias v 5 +7/8v lcd v 5 +6/8v lcd v 5 +2/8v lcd v 5 +1/8v lcd 1/9bias v 5 +8/9v lcd v 5 +7/9v lcd v 5 +2/9v lcd v 5 +1/9v lcd 1/10bias v 5 +9/10v lcd v 5 +8/10v lcd v 5 +2/10v lcd v 5 +1/10v lcd 1/11bias v 5 +10/11v lcd v 5 +9/11v lcd v 5 +2/11v lcd v 5 +1/11v lcd 1/12bias v 5 +11/12v lcd v 5 +10/12v lcd v 5 +2/12v lcd v 5 +1/12v lcd 1/13bias v 5 +12/13v lcd v 5 +11/13v lcd v 5 +2/13v lcd v 5 +1/13v lcd 1/14bias v 5 +13/14v lcd v 5 +12/14v lcd v 5 +2/14v lcd v 5 +1/14v lcd 48 47 46 45 44 v 1 v 2 v 3 v 4 v 5 power (v lcd =v dd -v 5 ) 41 40 39 38 37 36 35 34 c1 + c1 - c2 + c2 - c3 - c4 - c5 - c6 - o capacitor connecting terminals for internal voltage booster. boosting time is programmed by instruction (2 to 7 times ) 33 v out o boosted voltage output terminal. connects the capacitor between v out terminal and v ss . 43 vr i v lcd voltage adjustment terminal. the gain of vlcd setup circuit for v5 level is adjusted by external resistors. 16 ? 23 (22,23) d 0 ? d 7 (scl, si) i/o data input/output terminals. in pararel interface mode (ps 1 ="h", ps 0 ="h"/?l?) ? 8-bit bus mode* 1 : i/o terminals of 8-bit bus. ? 16-bit bus mode* 1 : i/o terminals of lower 8-bit of 16-bit bus * 1 8-bit or 16-bit bus is set by the ?8-bit / 16-bit bus select? instruction in serial interface mode(ps 1 ="l", ps 0 ="h"/?l?) ? d 7 : input terminal of serial data ( si ). ? d 6 : input terminal of serial data clock ( scl ). d0 to d5 terminals are hi-impedance when cs=?h?, d 0 to d 7 terminals are hi-impedance. 24 ? 30 d 8 ? d 15 i/o data input/output terminals in 16-bit bus interface mode (ps 1 ="h", ps 0 ="h"/?l?) ? i/o terminals of upper 8-bit of 16-bit bus. in 8-bit bus or serial interface mode ? d 8 to d 15 terminals are hi-impedance
NJU6682 no. symbol i/o description data discremination signal input terminal. the signal from mpu discreminates transmoitted data between display data and instruction. a0 h l distin. display data instruction 13 a0 i 8 res i reset terminal. when the res terminal goes to ?l?, the initialization is performed. reset operation is executing during ?l? state of res. 12 cs i chip select signal input terminal. data input/output are available during cs=?l?. rd i rd(80 type) or e(68 type) signal input terminal. ? in 80 type mpu mode ( ps 1 =?h?, sel68=?l? ) rd signal from 80 type mpu input terminal. active ?l?. d 0 to d 7 terminals are output during ?l? level. 15 (e) i ? in 68 type mpu mode ( ps 1 =?h?, sel68=?h? ) enable signal from 68 type mpu input terminal. active ?h?. wr i wr(80 type) or r/w(68 type) signal input terminal ? in 80 type mpu mode ( ps 1 =?h?, sel68=?l? ) wr signal from 80 type mpu input terminal. active ?l?. the data transmitted during wr=?l? are fetched at the rising edge of wr. ? in 68 type mpu mode ( ps 1 =?h?, sel68=?h? ) r/w signal from 68 type mpu input terminal . r/w h l state read write 14 (r/w) mpu interface type selection terminal. this terminal must connect to v dd or v ss . sel68 h l state 68 type 80 type 7 sel68 i 6 5 ps 0 ps 1 i parallel or serial interface selection signal input terminal. ps 1 ps 0 interface chip select data/ instruction data read/ write serial clock h l/h parallel cs a0 d 0 ? d 7 , d 8 ? d 15 rd,wr - h serial 4-wire cs a0 si(d 7 ) - scl(d 6 ) l l serial 3-wire cs every 17th data of serial data is recognized as a0. si(d 7 ) - scl(d 6 ) in case of serial interface( ps 1 =?l?,ps 0 =?h/l? ), rd and wr terminals must fix to ?h? or ?l?. d 0 to d 5 and d 8 to d 15 terminals are hi-impedance. 10 11 osc 1 osc 2 i/o external clock input terminal. in internal oscillation operation, osc 1 and osc 2 terminals should be open. in external clock operation, the external clock input to osc 1 terminal.
NJU6682 no. symbol i/o function 50 ? 209 c 0 ? c 159 o lcd driving signal output terminal. ? common output terminal: c 0 to c 159 ? segment output terminal: s 0 to s 131 ? common output terminal following output voltage is selected by the combination of alternating (fr) signal and common scanning data. scanning data altern ating (fr) common terminal output voltage h v 5 h l v dd h v 1 l l v 4 341 ? 210 s 0 ? s 131 o ? segment output terminal following output voltage is selected by the combination of alternating (fr) signal and display data in the dd ram. segment terminal output voltage scanning data altern ating (fr) normal display reverse display h v dd v 2 h l v 5 v 3 h v 2 v dd l l v 3 v 5
NJU6682 functional description (1) description of each blocks (1-1) busy flag (bf) the busy flag (bf) is set to logical ?1? in busy of internal execution by an instruction, and any instruction excepting for the ?status read? is disable at this time. busy flag is outputted through d 7 terminal by ?status read? instruction. although another instructions should be inputted after check of busy flag, no need to check busy flag if the system cycle time (t cyc ) as shown in ?ac characteristics? is secured completely. (1-2) display start line register the display start line register is a register to set a display data ram address corresponding to the com 0 display line (the top line normally) for the vertical scroll on the lcd, row address change and so forth. the display start line address set instruction sets the 9-bit display start address into this register. (1-3) line counter line counter is reset when the internal fr signal is switched and outputs the line address of the display data ram by count up operation synchronizing with common cycle of NJU6682 . (1-4) column address counter column address counter is the 6-bit preset-able counter to point the column address of the display data ram (dd ram) as shown in figure 1-1 and 1-2. the counter is incremented automatically after the display data read/write instructions execution. when the column address counter reaches to the maximum existing address by the increment operations, the count up operation (increment) is frozen. however, when new address is set to the column address counter again, it restarts the count up operation from a set address. the operation of column address counter is independent against row address register. by the address inverse instruction (adc select) as shown in figure 1-1 and 1-2, column address decoder reverses the correspondence between column address and segment output of display data ram. (1-5) row address register row address register assigns the row address of the display data ram as shown in figure 1-1 and 1-2. in case of accessing from the mpu with changing the row address, row address set instruction is required. (1-6) display data ram (dd ram) the display data ram (dd ram) is the bit map ram consisting of 84,480 bits to store the display data corresponding to the lcd pixel on lcd panel. each lcd pixel corresponds to two bits in the display data ram in gray scale mode and to one bit in black & white mode, display data respectively. the dd ram data : "00" = gray scale level 0 ( set by the ?gray scale level select? instruction) the dd ram data : "01" = gray scale level 1 ( ? ) the dd ram data : "10" = gray scale level 2 ( ? ) the dd ram data : "11" = gray scale level 3 ( ? ) the dd ram data and the state of the lcd in black & white mode: in normal display : "1"=turn-on display, "0" =turn-off display in reveres display : "1"=turn-off display, "0" =turn-on display the bus length accessing to the dd ram is chosen 8-bit access or 16-bit by the 8-bit/16-bit bus select instruction. in case of the 16-bit bus length is selected in the gray scale display mode, only upper 8 bits of column address are valid and lower 8 bits (d 7 -d 0 ) are ignored (fig. 1-1) because of 8-bit addressing ram area of column address=10 h . when the 16-bit bus length in the black & white display mode is selected, only upper 4 bits of column address are valid and lower 12 bit (d 11 -d 0 ) is ignored because of 4-bit ram area of column address=08 h (layer0) or column address=28 h (layer1) when the 8-bit bus length in the black & white display mode is selected, the dd ram is addressed by only upper 4 bits of column address thus lower 4 bits are also ignored. dd ram output 132 x 2 bits parallel data addressed by line counter then the data latched in the display data latch. asynchronous data access to the dd ram is available due to the access to the dd ram from the mpu and latch to the display data latch operation are done independently.
NJU6682 fig.1-1 dd ram addressing (gray scale mode) 0f h ( 001111 ) d3 01 02 03 04 06 05 07 08 09 0a 0b 0c 0e 0d 0f 10 11 12 138 139 13a 13b 13c 13e 13d 13f segment output 0 1 2 3 4 5 6 7 131 130 129 128 127 126 125 124 row address 00 column address adc=0 adc=1 00 h (000000) d7 d6 d5 d4 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15 d9 d8 d0 d1 d2 d4 d5 d6 d7 d10 d11 d12 d13 d14 d15 d9 d8 d10 d11 d12 d13 d14 d15 d9 d8 10 h (010000) d10 d11 d12 d13 d14 d15 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15 d9 d8 10 h ( 010000 ) 0f h (001111) d0 d1 d2 d3 d4 d5 d6 d7 d10 d11 d12 d13 d14 d15 d9 d8 00 h ( 000000 )
NJU6682 fig.1-2 dd ram addressing (black & white mode) 02 03 04 06 05 07 08 09 0a 0b 0c 0e 0d 0f 10 11 12 138 139 13a 13b 13c 13e 13d 13f 0 124 1 2 3 4 5 6 7 125 126 127 128 129 130 131 0 124 row address 00 01 1 2 3 4 5 6 7 125 126 127 128 129 130 layer 0 layer 1 column address adc=0 adc=1 00 h ( 000000 ) d15 d7 d6 d5 d4 d3 d2 d1 d0 d10 d11 d12 d13 d14 d9 d8 d0 d1 d2 d3 d4 d5 d6 d7 d12 d13 d14 d15 d10 d11 d12 d13 d14 d15 d9 d8 07 h (000111) d10 d11 d12 d13 d14 d15 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d12 d13 d14 d15 08 h (001000) 07 h ( 000111 ) d0 d1 d2 d3 d4 d5 d6 d7 d10 d11 d12 d13 d14 d15 d9 d8 00 h (000000) 08 h (001000) 20 h ( 100000 ) d7 d6 d5 d4 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15 d9 d8 d12 d13 d0 d1 d2 d3 d4 d5 d6 d7 d14 d15 d10 d11 d12 d13 d14 d15 d9 d8 27 h (100111) d10 d11 d12 d13 d14 d15 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d12 d13 d14 d15 28 h (101000) 27 h ( 100111 ) d0 d1 d2 d3 d4 d5 d6 d7 d10 d11 d12 d13 d14 d15 d9 d8 20 h (100000) 28 h (101000) segment output
NJU6682 ( 1 - 7 ) o utput a ss i gn m ent regi s t er t his c i r c uit dete r m i nes the sc anning di r e c t ion of the c o m m on output. t ab l e 1 s c anning di r e c t ion of the c o m m on output co m m on o u tput t e r m inal p a d no. 50 209 t e r m inal na m e c 0 c 159 v e r . a com 0 co m 159 v e r . b com 159 co m 0 * t he ma s k f i x es the c o m m on sc anning di r e c t ion bet w een ve r s ion a and b that c an not be c hanged by the in s t r u c t ion. ( 1 - 8 ) r e s e t c i r c u i t w hen the input s i gnal to res te r m inal goes to ? l ? , the r e s et c i r c uit e x e c utes initiali z ation as belo w ; - t he initiali z ation s t ate ( de f ault) 1. di s play m ode: 4 level g r ay s c ale di s play mode. 2. di s play o f f 3. no r m al di s play ( not inve r s e) 4 . a d c s e l e c t s: n o r m a l 5. read modi f y w r ite o f f 6. voltage boo s ter o ff , voltage regulator o ff , voltage f ollo w er o f f 7. w hole di s play / no r m al di s play 8. d r iver output o f f 9. clear the data of s e r i al inte r f a c e r egi s t er 10. set the colu m n add r e s s counter to 00 h 11. set the row add r e s s regi s ter to 00 h 12. set the sta r t line add r e s s to 00 h 13 . s e t t h e g r a y s c a l e l e v e l t o d e f a u l t v a l u e ( r e f er to ( 2 - 1 ) d e s c r iptions of the in s t r u c t ion codes ( n ) s ele c t g r ay s c ale level) 14. t he c ontinuous addre ss i ng of ddram (variable ram mapping mode o ff ) 15. set the evr r egi s t er to f f h 16. set the duty ratio to 1/160 17. bias s ele c t d 3 , d 2 , d 1 , d 0 = "1,0,1,0" (1/14 bia s ) 18. voltage boo s ter sele c t d 2 , d 1 , d 0 = "1,0,1" (7 ti m e s ) 19. set n - line inve r s e r egi s t er to 0 h 20. set to 8 - bit bus inte r f a c e m ode t he res te r m inal c o n ne c ts to t he r e s et te r m inal of the mpu s y n c h r o n i z a t ion w i t h t he m p u i n it i a l i z at i on as s h o w n in " the mpu i nte r f a c e " i n t he ap p li c a t i o n c i r c uit s e c t i o n. t he ? l? l e v e l i np u t s i gn a l a s r e s et s i g nal m u s t k eep t h e pe r i o d over t h an 1 0 us as s h o w n i n dc cha r a c te r i s t i cs . t he nju6 6 8 2 ta k es 1us f or the r e s et ope r a t ion a f ter the r i s i ng ed g e of the res s i gnal. t he r e s et ope r at i on b y r e s = ? l? i ni t i a l i zes e a c h r e s i s t er s etti n g as ab o ve r e s et s t atu s , b ut t he in t e r n a l o s c il l at i on c i r c uit and output te r m inals ( d 0 to d 15 ) a r e not a ff e c t ed. t o avoid the lo c k - up, the r e s et ope r ation by the res te r m inal m u s t be r equi r ed eve r y ti m e w hen po w er te r ns on. note1) t he r e s et ope r ation by the r e s et in s t r u c t ion, f un c tion 9 to 20 ope r ations m entioned above is pe r f o r m ed. note2) t he n o i s e in t o t he r e s t e r m inal s h o u l d b e eli m inat e d t o a v oid t h e e rr or on t h e a p p li c a t ion with the c a r e f ul de s ign. note3) t he r e s te r m inal m u s t be k eep ? l? lev e l w he n the po w er te r ns o n in not u s e of the b u ilt - i n lcd p o wer s upply c i r c uit f or no a ff e c t to the inte r nal e x e c ution.
NJU6682 (1-9) lcd driving circuit (a) lcd driver lcd driver is 292 sets of multiplexer consisting of 160 commons and 132 segments drivers to output the 4-level of lcd driving voltage. the common driver outputs the common scan signals formed with the shift register. the segment driver outputs the segment driving signal determined by a combination of display data in the dd ram, common timing, fr signal, and alternating signal for lcd. the output wave forms of segment/common are shown in ?lcd driving wave form?. (b) display data latch circuit display data latch circuit latches the 132 x 2-bit display data outputted from the dd ram addressed by the line address counter to lcd driver at every common signal cycle temporarily. the original data in the dd ram is not changed because of the normal/reverse display in black & white display mode, display on/off, whole display / normal display instruction processes only stored data in this display data latch circuit. (c) gray scale / black & white control circuit the gray scale control circuit selects the gray scale level data pointed by instruction out of 264 bits display data of the gray scale level signal in display data latch circuit and outputs to lcd driver sn. the black & white display control circuit selects a layer set by the instruction out of the 264 bits black & white data latched in display data latch circuit and outputs to the lcd driver sn. (d) signal forming to line counter and display data latch circuit the count clock to line counter and the latch clock to display data latch circuit are formed using the internal display clock (cl). the display data of 132 x 2 bits from display data ram pointed by the line address synchronizing with the internal display clock are latched into the display data latch circuit and are outputted to gray scale control circuit / black & white control circuit. the display data read out operation from dd ram to the lcd driver circuit is completely independent operation with an access to the display data ram from mpu. (e) display timing generation circuit the display timing generation circuit generates the internal timing of the display system by the master clock and the internal fr signal. as for it, the internal fr signal and the lcd alternating signal generate the wave form of 2-frame alternating drive wave form or the n-line inverse drive method for the lcd driving circuit. (f) frc / pwm control circuit the frc/pwm control circuit operates functions of frame rate control (frc) and pulse width modulation (pwm) for the 4-level gray scale display.
NJU6682 (g) common timing generator the common timing generator generates the common timing signal from the internal display clock (cl ). figure 2 shows display timing in black & white mode. fig.2-1 2-frame alternating drive mode (line inverting register sets to 0) fig.2-2 n-line inverse drive mode (n=7, line inverting register sets to 6) cl fr c0 c1 ram data sn 159 160 1 2 3 4 5 6 7 8 158 159 160 1 2 3 4 5 6 7 vdd vdd vdd v1 v1 v4 v2 v4 v5 v5 v5 v3 cl fr c0 c1 ram data sn 159 160 1 2 3 4 5 6 7 8 158 159 160 1 2 3 4 5 6 7 vdd vdd vdd v1 v1 v4 v2 v4 v5 v5 v5 v3
NJU6682 (h) oscillation circuits the oscillation circuit is a low power type cr oscillator using an internal resistor and capacitor. the oscillator output is using for the display timing clock and for the voltage booster circuit. and the display clock(cl) is generated from this oscillator output frequency by dividing. table 2 relationship between duty ratio and dividing duty 1/4 1/8 1/12 1/16 1/20 1/24 1/28 1/32 1/36 1/40 1/44, 1/48 1/52, 1/56 divide 1/1200 1/600 1/405 1/300 1/240 1/195 1/165 1/150 1/135 1/120 1/105 1/90 duty 1/60, 1/64, 1/68 1/72, 1/76, 1/80, 1/84, 1/88 1/92, 1/96, 1/100, 1/104, 1/108, 1/112, 1/116, 1/120 divide 1/75 1/60 1/45 duty 1/124, 1/128, 1/132, 1/136, 1/140, 1/144, 1/148, 1/152, 1/156, 1/160 divide 1/30 (i) power supply circuits the internal power supply circuit generates the voltage for driving lcd. it consists of voltage booster circuits (from 2 times to 7 times), voltage adjust circuits, and voltage followers. the internal power supply circuits is designed specially for a small-size lcd like as normal cellular phone size lcd panel. when NJU6682 apply to the large size lcd panel application (large capacitive load), external power supply is required to keep good display condition.. to keep good display condition, external component of the capacitors connecting to the v 1 to v 5 terminals and voltage booster circuits and the feedback resistors for the v 5 operational amplifier must fix each optimized constant after checking various display patterns on lcd panel actually in the application. the internal power supply circuits operation is controlled by internal power supply control instruction. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 0 0 0 1 * * * * * dc vr vf *:don?t care dc : voltage booster circuit dc = 1 : booster circuit on dc = 0 : booster circuit off (in this time , terminals c 1 + ,c 1 - ,c 2 + ,c 2 - ,c 3 - ,c 4 - ,c 5 - and c 6 - should be open and lcd driving voltage should be supplied to v out terminal from outside) vr : voltage adjust circuit vr = 1 : adjust circuit on vr = 0 : adjust circuit off (in this time, terminal vr should be open, and v 5 should be supplied from outside) vf : voltage follower vf = 1 : voltage follower on vf = 0 : voltage follower off (in this time, lcd bias voltage v 1 to v 5 should be supplied to terminals v 1 to v 5 from outside. )
NJU6682 ! power supply circuits example (1) internal power supply example (2) external power supply example all of the internal booster, voltage adjust circuit, only v out supply from outside, voltage follower using. int. voltage adjust circuit, voltage follower using. (dc, vr, vf) = (1, 1, 1) (dc, vr, vf) = (0, 1, 1) (3) external power supply example (4) external power supply example v out and v 5 supply from outside, all of v 1 to v 5 and v out supply from outside. internal voltage follower using. (dc, vr, vf) = (0, 0, 1) (dc, vr, vf) = (0, 0, 0) (note) : these switches should be open or external power supply stops in power-save mode. v dd v out v 1 v 2 v 4 v 3 v 5 v ss NJU6682 v dd v out v 1 v 2 v 4 v 3 v 5 v ss NJU6682 + + + + + + c 1 + + + + + + + c 2 + c 3 - c 4 - c 5 - c 6 - c 1 - c 2 - v dd v r v 5 v dd v out v 1 v 2 v 4 v 3 v 5 v ss NJU6682 + + + + + v dd v r v 5 v dd v out v 1 v 2 v 4 v 3 v 5 v ss NJU6682 + + + +
NJU6682 (2) instructions the NJU6682 distinguishes the data on the data bus d 0 to d 15 as an instruction by combination of a0, rd, and wr signals. the decoding of the instruction and exection performes with only high speed internal timing without relation to the external clock. in case of the serial interface, the data input as msb(d 15 ) first serially. table.3 shows the instruction codes of the NJU6682 table 3. instruction codes (*:don?t care) code instruction a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 description (a) display on/off 0 1 0 0 0 0 0 0 0 0 0 * 0/1 lcd display on/off d 0 =0:off, d 0 =1:on (b) display start line address set 0 1 0 0 0 1 0 1 0 1 line address determine the line address of dd ram to the com 0 (c) column address set 0 1 0 0 0 1 0 0 0 0 0 * * column address set the column address of dd ram (d) row address set 0 1 0 0 0 1 0 1 0 0 row address set the row address of dd ram (e) status read 0 0 1 status 0 status 0 read out the internal status (f) write display data 1 1 0 write data write the data into the dd ram (g) read display data 1 0 1 read data read out the data from the dd ram (h) normal or inverse display 0 1 0 0 0 0 0 0 0 0 1 * 0/1 normal or inverse display d 0 =0:normal, d 0 =1:inverse (i) whole display/ normal display 0 1 0 0 0 0 0 0 0 1 0 * 0/1 whole display turns on d 0 =0:normal, d 0 =1:whole display on 0 1 0 0 0 1 1 0 0 0 0 * start unit of 1 st block set the display start unit of block1 0 1 0 0 0 1 1 0 0 0 1 * number of unit in 1 st block set the number of display unit in block1 0 1 0 0 0 1 1 0 0 1 0 * start unit of 2 nd block set the display start unit of block2 0 1 0 0 0 1 1 0 0 1 1 * number of unit in 2 nd block set the number of display unit in block2 (j) partial display 0 1 0 0 0 1 1 0 1 0 0 * 0 execute the partial display (k) n-line inverse register set 0 1 0 0 0 0 0 0 0 1 1 * the number of n-line inverse set the n-line inverse number (l) evr register set 0 1 0 0 0 0 0 1 0 0 0 evr register data set the v 5 output level to the evr register 0 1 0 0 1 0 0 0 0 0 row address of 1 st display block set the row address of 1 st display block 0 1 0 0 1 0 0 0 0 1 0 * line number of 1 st block set the line number of 1 st display block 0 1 0 0 1 0 0 0 1 0 row address of 2 nd display block set the row address of 2 nd display block 0 1 0 0 1 0 0 0 1 1 0 * line number of 2 nd block set the line number of 2 nd display block 0 1 0 0 1 0 0 1 0 0 row address of 3 rd display block set the row address of 3 rd display block 0 1 0 0 1 0 0 1 0 1 0 * line number of 3 rd block set the line number of 3 rd display block 0 1 0 0 1 0 0 1 1 0 row address of 4 th display block set the row address of 4 th display block 0 1 0 0 1 0 0 1 1 1 0 * line number of 4 th block set the line number of 4 th display block 0 1 0 0 1 0 1 0 0 0 row address of 5 th display block set the row address of 5 th display block 0 1 0 0 1 0 1 0 0 1 0 * line number of 5 th block set the line number of 5 th display block 0 1 0 0 1 0 1 0 1 0 row address of 6 th display block set the row address of 6 th display block 0 1 0 0 1 0 1 0 1 1 0 * line number of 6 th block set the line number of 6 th display block 0 1 0 0 1 0 1 1 0 0 row address of 7 th display block set the row address of 7 th display block 0 1 0 0 1 0 1 1 0 1 0 * line number of 7 th block set the line number of 7 th display block 0 1 0 0 1 0 1 1 1 0 row address of 8 th display block set the row address of 8 th display block 0 1 0 0 1 0 1 1 1 1 0 * line number of 8 th block set the line number of 8 th display block (m) variable ram mapping mode 0 1 0 0 1 1 0 0 0 0 0 * 0/1 variable ram mapping mode d 0 =0:on, d 0 =1:off
NJU6682 code instruction a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 description 0 1 0 0 1 1 1 0 0 0 0 pwm data (1 st frame) pwm data (2 nd frame) gray scale level 0: set the pwm data for 1 st and 2 nd frames 0 1 0 0 1 1 1 0 0 0 1 pwm data (3 rd frame) pwm data (4 th frame) gray scale level 0: set the pwm data for 3 rd and 4 th frames 0 1 0 0 1 1 1 0 0 1 0 pwm data (1 st frame) pwm data (2 nd frame) gray scale level 1: set the pwm data for 1 st and 2 nd frames 0 1 0 0 1 1 1 0 0 1 1 pwm data (3 rd frame) pwm data (4 th frame) gray scale level 1: set the pwm data for 3 rd and 4 th frames 0 1 0 0 1 1 1 0 1 0 0 pwm data (1 st frame) pwm data (2 nd frame) gray scale level 2: set the pwm data for 1 st and 2 nd frames 0 1 0 0 1 1 1 0 1 0 1 pwm data (3 rd frame) pwm data (4 th frame) gray scale level 2: set the pwm data for 3 rd and 4 th frames 0 1 0 0 1 1 1 0 1 1 0 pwm data (1 st frame) pwm data (2 nd frame) gray scale level 3: set the pwm data for 1 st and 2 nd frames (n) select gray scale level 0 1 0 0 1 1 1 0 1 1 1 pwm data (3 rd frame) pwm data (4 th frame) gray scale level 3: set the pwm data for 3 rd and 4 th frames (o) bias select 0 1 0 0 0 0 0 1 0 0 1 * bias select the bias (11 types) (p) boost level select 0 1 0 0 0 0 0 1 0 1 0 * boost stage set the boost stage :2 to 7 times (q) read modify write /end 0 1 0 0 0 0 1 0 0 0 0 * 0/1 increase column address counter +1 whe n writing and no-change when reading d 0 =0:on, d 0 =1:end (r) reset 0 1 0 0 0 0 1 0 0 0 1 * 1 initialize the internal circuits (s) internal power supply setting 0 1 0 0 0 0 1 0 0 1 0 * dc vr vf dc=1: voltage booster on dc=0: voltage booster off vr=1: voltage regurator on vr=0: voltage regurator off vf=1: voltage follower on vf=0: voltage follower off (t) lcd driver outputs on/off 0 1 0 0 0 0 1 0 0 1 1 * 0/1 lcd driving wave form outputs on/off d 0 =0: lcd driver outputs off d 0 =1: lcd driver outputs on (u) power save (complex instruction) 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 * 0/1 set the power save mode (display off + static drive on) (v) adc select 0 1 0 0 0 0 1 1 0 0 0 * 0/1 output the display ram address sn d 0 =0:normal, d 0 =1:inverse (w) display mode select 0 1 0 0 0 0 1 1 0 0 1 * gs l1 l0 set display mode gb=1: gray scale mode gb=0: black and white mode l1=1: select layer 1 l1=0: not select layer 1 l0=1: select layer 0 l0=0: not select layer 0 (x) 8-/16-bit bus interface select 0 1 0 0 0 0 1 1 0 1 0/1 * d 8 =0: set 8-bit bus interface d 8 =1: set 16-bit bus interface ( *: don?t care)
NJU6682 (2-1) descriptions of the instruction codes (a) display on/off control it executes the on/off control of the whole display without relation to the dd ram or any internal conditions. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 0 0 0 0 * * * * * * * d *:don?t care d 0: display off 1: display on (b) display start line address set (refer to ?functional description fig. 1-1,1-2 dd ram addressing?) it sets the dd ram line address corresponding to the com 0 terminal (normally assigned to the top display line). in this instruction execution, the display area is automatically set by the lines that correspond to the display duty ratio to the upward direction of the line address. changing the line address by this instruction performs smooth scrolling to a vertical direction. in this time, the dd ram data are unchanged. when variable ram mapping mode is selected, this variable ram mapping setting takes precedence over the line address setting and line address set instruction is ignored. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 1 0 1 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 start line address (hex) 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 1 001 : : : : : : 1 0 0 1 1 1 1 1 0 13e 1 0 0 1 1 1 1 1 1 13f
NJU6682 (c) column address set (refer to ?functional description fig. 1-1,1-2 dd ram addressing?) when mpu access to the dd ram, a column address is set by column address set instruction before writing the data. the dd ram becomes accessible by setting both of column address and row address. (note: the change of row address is not affected to the display.) the range of column address is determined by the display mode. in gray scale mode, the range of column address is 00 h to 10 h . in black & white mode, 00 h to 08 h (layer 0) and 20 h to 28 h (layer 1). over range of column address setting is ignored. when the mpu access to the dd ram continuously, the column address increments automatically from the set address after each data access. therefore, the mpu can transmit only the data continuously without setting the column address at every transmission time. the increment of column address is stopped at the maximum column address plus 1 limited by each display mode. when the column address count up is stopped, the row address is not changed. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 0 0 0 0 * * a 5 a 4 a 3 a 2 a 1 a 0 *:don?t care column address (hex) a 5 a 4 a 3 a 2 a 1 a 0 gray scale mode black & white mode 0 0 0 0 0 0 00 00 0 0 0 0 0 1 01 01 0 0 0 0 1 0 02 02 : : : : : : 0 0 1 0 0 0 : layer 0 08 : : 0 0 1 1 1 0 0e 0 0 1 1 1 1 0f 0 1 0 0 0 0 10 : : : : address set is invalid 1 0 0 0 0 0 20 1 0 0 0 0 1 21 : : 1 0 0 1 1 1 27 1 0 1 0 0 0 layer 1 28 : : : address set is invalid address set is invalid
NJU6682 (d) row address set (refer to ?functional description fig. 1-1,1-2 dd ram addressing?) when mpu accesses to the dd ram , the row address set by row address set instruction is required with the (c) column address set before writing the data. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 1 0 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 row address (hex) 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 1 001 : : : : 1 0 0 1 1 1 1 1 0 13e 1 0 0 1 1 1 1 1 1 13f (e) status read this instruction reads out the intenal status of ?busy?, ?adc?, ?display on/off?, ?reset?, ?gb?, and ?ly? described as follows. even if 8-bit bus interface mode is selected, the status read instruction completes within one cycle only. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 busy adc on/off reset gb ly 1 ly 0 0 busy adc on/off reset gb ly 1 ly 0 0 busy : busy=1 indicates internal circuits is operating or the reset cycle. all instructions can be input after the busy status change to ?0?. adc : indidates the correspondence of column address and segment driver. 0: counterclockwise output (inverse) column address 131-n <--->segment driver n 1: clockwise output (normal) column address n <--->segment driver n (note) the data ?0=inverse? and ?1=normal? of adc status is inverted with the adc select instruction of ?1=inverse? and ?0=normal?. on/off : indicates the display on/off status. 0: display ?on? 1: display ?off? (note) the data ?0=on? and ?1=off? of display on/off status is inverted with the display on/off instruction of ?1=on? and ?0=off?. reset : indicates the initializing period by res terminal signal or reset instruction. 0: not reset status 1: in the reset status gb : indicates the current display mode. 0: black & white mode 1: gray scale mode ly 1 : indicates the status of layer 1 when the black & white display mode is selected. 0: layer 1 is not selected 1: layer 1 is selected ly 0 : indicates the status of layer 0 when the black & white display mode is selected. 0: layer 0 is not selected 1: layer 0 is selected
NJU6682 (f) write display data it writes the data on the data bus into the dd ram. column address increments automatically after data writing, therefore, the mpu can write the data into the dd ram continuously without the address setting at every writing time once the starting address is set. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 write data (g) read display data this instruction reads out the 16-bit data from dd ram addressed by the row and the column address. the column address automatically increments after the 16-bit data read out, therefore, the mpu can read the data from the dd ram continuously without the address setting at every reading time once the starting address is set. note that the dummy read is required just after setting the column address (see ?(5-4) access to the dd ram and the internal register?). in the serial interface mode, the display data is unable to read out. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 read data (h) normal / inverse display it changes the display condition of normal or inverse for entire display area. the execution of this instruction does not change the display data in the dd ram. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 0 0 0 1 * * * * * * * d *:don?t care black & white mode: d dd ram=?1? dd ram=?0? 0 (normal) lcd on lcd off 1 (inverse) lcd off lcd on gray scale mode: d dd ram=?00? dd ram=?01? dd ram=?10? dd ram=?11? 0 (normal) gray scale level 0 gray scale level 1 gray scale level 2 gray scale level 3 1 (inverse) gray scale level 3 gray scale level 2 gray scale level 1 gray scale level 0
NJU6682 (i) whole display / normal display this instruction turns all the pixels on regardless the data stored in the dd ram. in this time, the data in dd ram are remained and unchanged. this instruction is executed prior to the ?normal or inverse display? instruction. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 0 0 1 0 * * * * * * * d *:don?t care d 0: normal display 1: whole display turns on when the ?static drive on? instruction is executed at display off status, the NJU6682 operates in power save mode. (refer ? power save mode ?) (j) partial display it selects two active display areas on the lcd panel partially. the display area is divided to 40 units with four commons each and selected two display blocks by setting unit number and number of unit required (not overlap, not over than 40 units) to display on the lcd panel. these two display blocks are assigned optionally on the lcd panel. duty selects an adapted ratio number corresponding to the total number of two display blocks automatically. partial display function adjusts the lcd driving voltage, voltage boosting times and e.v.r level by the instruction to generate the optimum lcd driving voltage for display quality. as result, the operating current is reduced. - display unit structure unit 0 unit 1 unit 2 unit 3 : : : unit 36 unit 37 unit 38 unit 39 - partial display instruction when partial display functions, both of top unit number of display area (the start unit) and the number of the effective continuous unit (display unit) from the start unit for the first display block and the second. attention that the first display block and the second definition must not be overlap of display area and not be over than 40 units in total. in case of whole display (1/160 duty), the first display block defines start unit=0 (0,0,0,0,0,0) and display unit = 40 (1,0,1,0,0,0) for all of display area selection. in this time, the definition of the second display block is ignored. in case of only the first block display, the second display block defines start unit=0 (0,0,0,0,0,0) and display unit = 0 (0,0,0,0,0,0) for no display area. 4-common x 40-unit = 160-common maximum 132-segment
NJU6682 (1) set the start unit of the 1st partial display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 0 0 * * d d d d d d (2) set the display unit number of the 1st partial display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 0 1 * * d d d d d d (3) set the start unit of the 2nd partial display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 1 0 * * d d d d d d (4) set the display unit number of the 2nd partial display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 1 1 * * d d d d d d *:don?t care d : the start unit (d:000000 ? 100111), or the display unit number(000000 ? 101000) by input following instruction, the duty ratio is changed automatically and executes the partial display function. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 1 0 0 * * * * * * * 0 *:don?t care (notes) attention followings due to prevent from mulfunction. - the input order of partial display instructions must follow above. - prohibits the overlap of the 1st partial display block and the 2nd. - the start unit of the 1st partial display block must not be over 39. - the total display unit number (the sum of the 1st and 2nd partial display block unit number) must not be over 40. - on the lcd panel, no active display area inserts between the 1st display block and the 2nd . however, the display data of the 1st display block and the 2nd must store continuously in the display data ram.
NJU6682 example of the partial display setting. the above partial display condition is set as follows: (1) set the start unit of the 1st partial display block to ?0?. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 (2) set the display unit number of the 1st partial display block to ?2?. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 1 0 (3) set the start unit of the 2nd partial display block to ?14?. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 0 (4) set the display unit number of the 2nd partial display block to ?16?. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 (5) execute the partial display. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 the duty is changed to 1/72 automatically. ( duty = 1/unit x 4 ) duty is changed automatically when partial display execution. but lcd driving voltage, bias, driving form like as 2-frame alternating driving or n-line inverse are not changed. therefore, lcd driver output off should operate before partial display execution for prevention of unexpected display, and voltage booster select instruction, e.v.r register set, bias select and n-line inverse driving set should set optimum conditions for good display in the mean time of partial display instruction execution. the optimum conditions should fix refering the result of actual display eveluation. display area unit 0 unit 1 : unit 14 unit 15 : unit 28 unit 29 : the 2nd block the 1st block
NJU6682 the sequence about the partial display function (k) n-line inverse resister set (refer functional description fig.2-2 n-line inverse alternative driving wave form) it sets a line number to inverse the polarity lof common driver and segment. set a n-line inverse resister a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 0 0 1 1 * * a 5 a 4 a 3 a 2 a 1 a 0 *:don?t care a 5 a 4 a 3 a 2 a 1 a 0 inverse line 0 0 0 0 0 0 -(*) 0 0 0 0 0 1 2 0 0 0 0 1 0 3 : : : : 1 1 1 1 1 0 63 1 1 1 1 1 1 64 *when a 5 to a 0 are ?000000?, it set to 2-frame alternating drive mode. evr resister set set a start unit of the first display unit set a number of display unit of the first set a start unit of the second display unit set a number of display unit of the second executes partial display function partial display instruction (*) 2-frame alternating drive mode . driver output off n-line inverse set bias select voltage boosting driver outputs on (waiting time)
NJU6682 (l) evr resister set it controls the voltage regulator circuit of the internal lcd power supply to adjust the lcd display contrast by changing the lcd driving voltage ?v 5 ?. by data setting into the evr register, the lcd driving voltage ?v 5 ? selects out of 201 steps of regulated voltage. the voltage adjustable range of ?v 5 ? is fixed by the external resistors. for details, refer the section ?4-2) voltage adjust circuit?. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 1 0 0 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v lcd 0 0 1 1 0 1 1 1 low : : : : 1 1 1 1 1 1 1 0 : 1 1 1 1 1 1 1 1 high v lcd =v dd -v 5 set the evr register to ff h (1,1,1,1,1,1,1,1), if not use the evr.
NJU6682 (m) variable ram mapping mode in the variable ram mapping mode, independent 8 blocks can be defined in the dd ram. the variable ram mapping functions to assign the ram data unconsecutively selectable out of the above 8 blocks (at the maximum); therefore, replacing one part of the display data to another becomes easier (see figure 3-1, 3-2, 4-1 and 4-2). it is possible to define the ram area in a maximum of 8-blocks not to continue to display the screen. therefore, it is easy to replace a part of the display data each other(fig.3-1,3-2, 4-1,4-2). in the variable ram mapping mode, display start line address determined by ?2-1 (b) start line address set instruction? instruction becomes invalid, thus the vertical scroll function also becomes invalid with changing a line address will be unable. the number of the display line for each block is assignable from ?1? to ?63?; ?0? is invalid in this command. and, it is available to define the display line number of each blocks as, but it must not define as ?0?. if the total number of the display line exceeds the duty, the line data in excess of its duty is not displayed. the initialized state of the resistor regarding the variable ram mapping is indefinite after reset. fig.3-1 setup the variable ram mapping mode, and address map in the dd ram fig.3-2 actual display image 1st block row address a b c d e f g a b c d e f g 2nd block row address 3rd block row address 4th block row address 5th block row address 6th block row address 7th block row address 1st block display line number 2nd block display line number 3rd block dis p la y line number 7th block display line number 4th block display line number 5th block display line number 6th block display line number h 8th block row address 8th block display line number h
NJU6682 the example of variable ram mapping mode fig.4-1 the setup of variable ram mapping mode, and the address map fig.4-2 the actual display image when the 2nd block row-address is changed like the sequence o f ?80? h -> ?100? h -> ?80? h a b c a b d a b c 1st block row address a b 3rd block row address row address=80h 1st block display line number 3rd block display line number c d row address=100h 2nd block
NJU6682 (1) set the row address of the 1st display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 0 0 0 a a a a a a a a a a: the row address of the 1st display block (0 to 319) (2) set the display line number of the 1st display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 0 0 1 0 * * d d d d d d *:don?t care d: the display line number of the 1st display block (1 to 63) (3) set the row address of the 2nd display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 0 1 0 a a a a a a a a a a: the row address of the 2nd display block (0 to 319) (4) set the display line number of the 2nd display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 0 1 1 0 * * d d d d d d *:don?t care d: the display line number of the 2nd display block (1 to 63) (5) set the row address of the 3rd display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 1 0 0 a a a a a a a a a a: the row address of the 3rd display block (0 to 319) (6) set the display line number of the 3rd display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 1 0 1 0 * * d d d d d d *:don?t care d: the display line number of the 3rd display block (1 to 63) (7) set the row address of the 4th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 1 1 0 a a a a a a a a a a: the row address of the 4th display block (0 to 319) (8) set the display line number of the 4th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 1 1 1 0 * * d d d d d d *:don?t care d: the display line number of the 4th display block (1 to 63)
NJU6682 (9) set the row address of the 5th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 0 0 0 a a a a a a a a a a: the row address of the 5th display block (0 to 319) (10) set the display line number of the 5th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 0 0 1 0 * * d d d d d d *:don?t care d5: the display line number of the 5th display block (1 to 63) (11) set the row address of the 6th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 0 1 0 a a a a a a a a a a: the row address of the 6th display block (0 to 319) (12) set the display line number of the 6th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 0 1 1 0 * * d d d d d d *:don?t care d: the display line number of the 6th display block (1 to 63) (13) set the row address of the 7th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 1 0 0 a a a a a a a a a a: the row address of the 7th display block (0 to 319) (14) set the display line number of the 7th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 1 0 1 0 * * d d d d d d *:don?t care d: the display line number of the 7th display block (1 to 63) (15) set the row address of the 8th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 1 1 0 a a a a a a a a a a: the row address of the 8th display block (0 to 319) (16) set the display line number of the 8th display block a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 1 1 1 1 0 * * d d d d d d *:don?t care d: the display line number of the 8th display block (1 to 63)
NJU6682 execute the variable ram mapping mode, by the following instruction. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 0 0 0 0 0 * * * * * * * 0 *:don?t care return to the normal display status from variable ram mapping mode by the following instruction execution. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 0 0 0 0 0 * * * * * * * 1 *:don?t care
NJU6682 (n) gray scale level select this instruction sets the 4 levels of the gray scale. the setting of each gray scale level is executed by writing the pwm data (0 to f h ) to the four registers for the 1st to 4th frame. the glay scale level 0 corresponds to the data (0,0) of the dd ram, the level 1 is the data (0,1), the level 2 is the data (1,0), and the level 3 is the data (1,1), respectively. after reset, 4 registers of each level of the gray scale, 16 registers totality, are initialized as follows. see the table below. pwm data hex gray scale level 0 00 0/15 (initialized value of level 0) 1 01 1/15 2 02 2/15 3 03 3/15 4 04 4/15 5 05 5/15 (initialized value of level 1) 6 06 6/15 7 07 7/15 8 08 8/15 9 09 9/15 10 0a 10/15 (initialized value of level 2) 11 0b 11/15 12 0c 12/15 13 0d 13/15 14 0e 14/15 15 0f 15/15 (initialized value of level 3) (1) set the 1st and 2nd frame pwm data for the gray scale level 0. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 0 d1 d1 d1 d1 d2 d2 d2 d2 d1: the pwm data for the 1st frame d2: the pwm data for the 2nd frame (2) set the 3rd and 4th frame pwm data for the gray scale level 0. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 0 1 d3 d3 d3 d3 d4 d4 d4 d4 d3: the pwm data for the 3rd frame d4: the pwm data for the 4th frame
NJU6682 (3) set the 1st and 2nd frame pwm data for the gray scale level 1. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 1 0 d1 d1 d1 d1 d2 d2 d2 d2 d1: the pwm data for the 1st frame d2: the pwm data for the 2nd frame (4) set the 3rd and 4th frame pwm data for the gray scale level 1. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 0 1 1 d3 d3 d3 d3 d4 d4 d4 d4 d3: the pwm data for the 3rd frame d4: the pwm data for the 4th frame (5) set the 1st and 2nd frame pwm data for the gray scale level 2. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 1 0 0 d1 d1 d1 d1 d2 d2 d2 d2 d1: the pwm data for the 1st frame d2: the pwm data for the 2nd frame (6) set the 3rd and 4th frame pwm data for the gray scale level 2. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 1 0 1 d3 d3 d3 d3 d4 d4 d4 d4 d3: the pwm data for the 3rd frame d4: the pwm data for the 4th frame (7) set the 1st and 2nd frame pwm data for the gray scale level 3. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 1 1 0 d1 d1 d1 d1 d2 d2 d2 d2 d1: the pwm data for the 1st frame d2: the pwm data for the 2nd frame (8) set the 3rd and 4th frame pwm data for the gray scale level 3. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 1 1 0 1 1 1 d3 d3 d3 d3 d4 d4 d4 d4 d3: the pwm data for the 3rd frame d4: the pwm data for the 4th frame
NJU6682 (o) bias select this instruction sets the bias voltage. ( 1/4 to 1/14 bias ) a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 1 0 0 1 * * * * a 3 a 2 a 1 a 0 *:don?t care a 3 a 2 a 1 a 0 bias 0 0 0 0 1/4 0 0 0 1 1/5 0 0 1 0 1/6 0 0 1 1 1/7 0 1 0 0 1/8 0 1 0 1 1/9 0 1 1 0 1/10 0 1 1 1 1/11 1 0 0 0 1/12 1 0 0 1 1/13 1 * 1 * 1/14 * : don?t care (p) boost level select this instruction sets the boost level (2 to 7 times). when ?partial display instruction? execution, the ?boost level select? also must be executed. if the external capasitors are connected as the lower than 6 times boost level, don?t set the boost level by the instruction over than the boost level by conecting capasitors. if set the boost level over than it, the device will make malfunction. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 1 0 1 0 * * * * * a 2 a1 a0 *:don?t care a 2 a 1 a 0 boost level 0 0 0 2-times 0 0 1 3-times 0 1 0 4-times 0 1 1 5-times 1 0 0 6-times 1 * 1 7-times * : don?t care (q) read modify write / end this instruction sets the read modify write/end controlling the page address increment. in this mode, the column address only increments when execute the display data ?write? instruction; but no change when the display data ?read? instruction. this status is continued until the end instruction execution. when the end instruction is executed, the column adddress goes back to the start address before the execution of this ?read modify write? instruction. this function reduces the load of mpu for repeating display data change of the fixed area (ex. cursor blink). a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 0 0 0 0 0 * * * * * * * d * : don?t care d=0: read modify write on d=1: end (note) in this ?read modify write? mode, out of display dara ?read?/?write?, any instructions except ?row address set? can be executed.
NJU6682 the example of read modify write sequence executed instructions row address set column address set read modify write ye s set the start address of the cursor display *1 column counter reset to the value of *1 start the read mdify write dummy read data read column counter does?t increase data write column counter increase the data is inversed at mpu the data is ignored write back the data read out the data end dummy read column counter doesn?t increase column counter doesn?t increase data read data write column counter increase dummy read data read data write dummy read data read data write end the read modify write finish ? no repeat the same sequence n n+1 n+2 n+3 n n+1 n+2 n+3 n n+1 n+2 n+3 n n+1 n+2 n+3 n n+1 n+2 n+3 n+4 n+4 n n+1 n+2 n+3 n+4 column counter does?t increase column counter doesn?t increase column counter doesn?t increase column counter doesn?t increase column counter doesn?t increase column counter increase column counter increase display contents (in 8-bit bus mode, indicates the column address) executed instructions
NJU6682 (r) reset this instruction executes the following initialization the reset by the reset signal input to the res terminal (hardware reset) is required when power turns on. this reset instruction does not use instead of this hardware reset when power turns on. initialization 1: clear the data in the selial interface register. 2: set the column address counter to 00 h . 3: set the row address resister to 000 h . 4: set the line address counter to 000 h 5: set the gray scale level ( refer to ?(n)) 6: normal ram address mapping (variable ram mapping mode off). 7: set the evr resister to ff h . 8: set the duty ratio to ?1/160?(all on). 9: set the bias ratio to ?1/14?. 10: set the booster level to 7 times. 11: set the n-line inverse register to 0 h . 12: set the 8-bit bus length for the interface the dd ram is not affected in this initialization. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 0 0 0 1 * * * * * * * d * : don?t care the dd ram is not affected in this instruction (s) internal power supply this instruction control on and off for the internal voltage converter, voltage regulator and voltage follower circuits. for the booster circuits operation, the oscillation circuits must be in operation. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 0 0 1 0 * * * * * dc vr vf * : don?t care dc=1: booster on dc=0: booster off*1) vr=1: voltage regulator on vr=0: voltage regulator off*2) vf=1: voltage follower on vf=0: voltage follower off*3) *1) at this time, terminals c 1 + ,c 1 - ,c 2 + ,c 3 - ,c 4 - ,c 5 - and c 6 - should be open, and supply the v out from outside. *2) at this time, terminal v r should be open, and supply the v 5 from outside. *3) at this time, bias voltage of v 1 to v 5 should be supplied from outside. *the internal power supply rise time is depending on the condition of the supply voltage, v lcd =v dd -v 5 , external capacitor of booster, and external capacitor connected to v 1 to v 5 . to know the rise time correctly, test by using the actual lcd module.
NJU6682 (t) driver outputs on/off this instruction controlls on/off of the lcd driver outputs. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 0 0 1 1 * * * * * * * d * : don?t care d=0: driver outputs off(signai is v dd level) d=1: driver outputs on (signal is output) the NJU6682 implements low power lcd driving voltage generator circuit and requires the following power supply on/off sequence. ? lcd driving power supply on/off sequences the sequences below are required when the power supply turns on/off. for the power supply turning on operation after the power-save mode, refer the (u) ?power save release sequence? mentioned after. ? turn on sequence ? turn off sequence *1 the internal power supply rise time is depending on the condition of the supply voltage, v lcd =v dd -v 5 , external capacitor of booster, and external capacitor connected to v 1 to v 5 . to know the rise time correctly, test by using the actual lcd module. evr resister set (wait time)*1 internal powe r supply on driver outputs on static drive on driver outputs off display off NJU6682 power off internal power supply off or external power supply off
NJU6682 (u) power save (complex comand) when whole display on at the display off status (inverse order also same), the internal circuits goes to the power save mode and the operating current is dramatically reduced, almost same as the standby current. the internal status in the power save mode is shown as follows; 1: the oscillation circuits and the internal power supply circuits stop the operation. 2: lcd driving is stopped. segment and common drivers output v dd level voltage. 3: the display data and the internal operating condition are remained and kept as just before enter the power save mode. 4: all the lcd driving bias voltage (v 1 to v 5 ) is fixed to the v dd level. ? power save sequence *1 ? power save release sequence *2 *1 in the power save sequence, the power save mode starts after the static drive on command is executed. *2 in the power save release sequence, the power save mode releases just after the static drive off instruction execution. the display on instruction is allowed to execute at any time after the static drive off instruction is completed. *3 the internal power supply rise time is depending on the condition of the supply voltage, v lcd =v dd -v 5 , external capacitor of booster, and external capacitor connected to v 1 to v 5 . to know the rise time correctly, test by using the actual lcd module *4 lcd driving waveform is output after the exection of the driver outputs on instruction execution. *5 in case of the external power supply operation, the external power supply should be turned off before the power save mode and connected to the v dd for fixing the voltage of vout terminal.. in this time, v out terminal also should be made codition like as connection to the v ss terminal. (v) adc select this instruction determines the correspondence of column address of the dd ram with the segment driver outputs.( refer to fig.1-1 dd ram addressing) segment driver output order is inverse when this instruction executes, therefore, the placement the NJU6682 against the lcd panel becomes easy. whole display on whole display off (wait time) *3 driver outputs on a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 1 0 0 0 * * * * * * * d *:don?t care d=0: clockwise output (normal) d=1: counterclockwise output (inverting) driver outputs off display off display on *4
NJU6682 (w) display mode select this instruction selects the display mode. (x) 8-/16-bit bus interface select this instruction selects the 8-bit or 16-bit bus interface length. a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 1 0 0 1 * * * * * gs l 1 l 0 *:don?t care gs=1: gray scale mode gs=0: black & white mode * when gs=0(black & white mode), the following l 1 and l 0 bit are valid. l 1 =1: select the layer 1 l 1 =0: not select the layer 1 l 0 =1: select the layer 0 l 0 =0: not select the layer 0 if l 1 =l 0 =0, the display data becomes 0 and if l1=l0=1, the display data becomes logical or of the layer 0 and layer 1. gs=1: gray scale mode a0 rd wr d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 1 0 1 d * * * * * * * * *:don?t care d=0: select 8-bit bus interface length (d 7 to d 0 ). d=1: select 16-bit bus interface length (d 15 to d 0 )
NJU6682 (4) internal power supply (4-1) 7-time voltage booster circuits the 7-time voltage booster circuit outputs the negative voltage(v dd common) boosted 7 times of v dd -v ss from the v out terminal with connecting the seven capacitors between c 1 + and c 1 - , c 2 + and c 2 - , c 1 + and c 3 - , c 2 + and c 4 - , c 1 + and c 5 - , c 2 + and c 6 - ,and v ss and v out . the boosting time is selected out of 2 times to 7 by the combination of changing the external capacitors connection and ?boost level select? instruction. (refer to (2)instruction (q)voltage boost time select) voltage booster circuits requires the clock signals from internal oscillation circuit or the external clock signal. therefore, the internal oscillation circuits or the external clock supplier must be operating when the voltage booster is in operation. the boosted voltage of v dd -v out must be 18v or less. the boost voltage and the capacitor connection are shown below. 7-times voltage 6-times voltage 5-times voltage 4-times voltage 3-times voltage 2-times voltage v dd =+3v v out =-v dd =-3v v ss =0v v out =-4v dd =-12v v out =-2v dd =-6v v out =-3v dd =-9v v out =-5v dd =-15v v out =-6v dd =-15v ; v dd =+2.5v for voltage limitation v dd =+2.5v + v ss v out c 1 + c 1 - c 2 + c 2 - c 3 - c 4 - c 5 - c 6 - + + + + + + v ss v out c 1 + c 1 - + c 2 + c 2 - c 3 - c 4 - c 5 - c 6 - + + + + + v ss v out c 1 + c 1 - + c 2 + c 2 - c 3 - c 4 - c 5 - c 6 - + + + + v ss v out c 1 + c 1 - + c 2 + c 2 - c 3 - c 4 - c 5 - c 6 - v ss v out c 1 + c 1 - + c 2 + c 2 - c 3 - c 4 - c 5 - c 6 - v ss v out c 1 + c 1 - + c 2 + c 2 - c 3 - c 4 - c 5 - c 6 - + + + + + + 2-times 3-times 4-times 5-times 6-times 7-times
NJU6682 (4-2)voltage adjust circuit the boosted voltage of v out outputs v 5 for lcd driving through the voltage adjust circuits. the output voltage of v 5 is adjusted by ra and rb within the range of |v 5 | < |v out |. the output is calculated by the following formula(1). v lcd =v dd -v 5 =(1+rb/ra)v reg ------------------------------------------(1) the v reg voltage is a reference voltage generated by the built-in bleeder registance. v reg is adjustable by evr functions (see section 4-3). for minor adjustment of v 5 , it is recommended that the ra and rb is composed of r 2 as variable resistor and r 1 and r 3 as fixed resistors, constant should be connected to v dd terminal,vr and v 5 ,as shown below. (refer to fig.5) fig.5 voltage adjust circuit < design example for r 1 , r 2 and r 3 /reference > ? r 1 +r 2 +r 3 =5m ? (determind by the current between v dd -v 5 ) ? variable voltage range by the r 2 . -7v to -11v (v lcd =v dd -v5 : 10v to 12v) (determind by the lcd electrical characteristics) ? v reg =3v (in case of v dd =3v and evr=ff h ) r 1 ,r 2 and r 3 are calculated by above conditions and the fomula of(1) to below; r1=1.5m ? r2=0.3m ? r3=4.2m ? note) v 5 voltage is generated referencing with v reg voltage beased on the supply voltage (v dd and v ss ) as shown in above figure 5. therefore, v lcd (v dd -v 5 ) is affected including the gain (rb/ra) by the fluctuation of v reg voltage based on the supply voltage. the power supply voltage should be stabilized for v 5 stable operation. + - rb ra v reg r 3 r 1 vr r 2 v out v 5 v dd
NJU6682 (4-3)contrast adjustment by the evr function the evr selects the v reg voltage out of the following 201 conditions by setting 8-bit data into the evr register. with the evr function, v reg is controlled, and the lcd display contrast is adjusted. the evr controls the voltage of v reg by instruction and changes the voltage of v 5 . a step with evr is set like table shown below. * if keeping 3 % precision set evr over 4f h . in use of the evr function, the voltage adjustment circuit must turn on by the power supply instruction. adjustable range of the lcd driving voltage by evr function the adjustable range is decided by the power supply voltage v dd and the ratio of external resistors ra and rb. < design example : NJU6682 > condition:v dd =3.0v ra=1m ? , rb=4m ? (ra:rb=1:4) the adjustable range and step voltage are calculated as follows in the above condition. in case of setting 4f h in the evr register, vlcd=(1+rb/ra) x v reg =(1+4) x (124/300) x 3.0 =6.2v in case of setting ff(h) in the evr register, vlcd=(1+rb/ra) x vreg =(1+4) x (300/300) x 3.0 =15.0v (min.)4f h (max.)ff h adjusutment renge ( v lcd ) 6.2 15.0 [ v ] step voltage ( v lcd ) 50 [ mv ] * in case of v dd =3v evr register v reg 37 h 38 h 39 h : : : : fd h fe h ff h (100/300) x (v dd -v ss ) (101/300) x (v dd -v ss ) (102/300) x (v dd -v ss ) : : : : (298/300) x (v dd -v ss ) (299/300) x (v dd -v ss ) (300/300) x (v dd -v ss )
NJU6682 (4-4)lcd driving voltage generation circuit the lcd driving bias voltage of v 1 ,v 2 ,v 3 ,v 4 are generated by dividing the v lcd (v lcd =v dd -v 5 ) voltage with the internal bleeder resistance and is supplied to the lcd driving circuits after the impedence conversion by the voltage follower. as shown in figure 6, five external capacitors are required to connect to each lcd driving voltage terminal for voltage stabilization. the value of capacitors (c 7 to c 11 ) should be determined after the actual lcd panel display evaluation. in case of internal power supply in case of using external power supply fig.6 lcd driving voltage generation circuit reference set up value v lcd =v dd -v 5 ? 9.0 to 10.5v cout to 1.0uf c1 to c6 to 1.0uf c7 to c11 0.1 to 0.47 uf r1 2m ? r2 500k ? r3 2.5m ? *1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. *2 following connection of v out is required when external power supply using. when v ss > v 5 --- v out =v 5 when v ss v 5 --- v out =v ss + + + + + v 1 v 2 v 4 v 3 v 5 vout vr v 5 v ss c 3 - c 4 - c 6 - c 5 - NJU6682 v dd r1 r2 *1 r3 c 7 c 8 c 10 c 9 c 11 + c 3 c 4 c 5 c 6 cout c 2 - c 2 + c 2 c 1 - c 1 + c 1 + + v 1 v 2 v 4 v 3 v 5 vout vr v 5 v ss c 3 - c 4 - c 6 - c 5 - NJU6682 v dd *2 c 2 - c 2 + c 1 - c 1 + external power supply + + + +
NJU6682 (5)mpu interface (5-1) interface type selection two mpu interface types are available in the NJU6682: by 1) 8/16-bit bi-directional data bus (d 15 to d 0 ), 2) serial data input (si:d 7 ). the interface type (the 8/16 bit parallel or serial interface) is determined by the condition of the ps 1 and ps 0 terminals connecting to "h" or "l" level as shown in table 5. in case of the parallel interface, the external bus line selection is set by the ?8-bit/16-bit bus select? instruction. in case of the serial interface, neither the status read-ou t nor the ram data read-out operation is allowed. table 5 ps 1 ps 0 type cs a0 rd wr sel68 d 15 ? d 8 d 7 d 6 d 5 ? d 0 8-bit bus cs a0 rd wr sel68 hi-z d 7 d 6 d 5 ? d 0 h * parallel 16-bit bus cs a0 rd wr sel68 d 15 ? d 8 d 7 d 6 d 5 ? d 0 h serial (4-wire) a0 l l serial (3-wire) cs * * * * hi-z si scl hi-z *:don?t care (5-2)parallel interface(ps 1 =?h?) the NJU6682 interfaces the 68- or 80-type mpu directly if the parallel interface (ps 1 ="h") is selected. the 68-type or 80-type mpu is selected by connecting the sel68 terminal to "h" or "l" as shown in table 6. table 6 sel68 type cs a0 rd wr d 15 ? d 8 d 7 ? d 0 h 68 type mpu cs a0 e r/w d 15 ? d 8 d 7 ? d 0 l 80 type mpu cs a0 rd wr d 15 ? d 8 d 7 ? d 0 - interface operation with mpu the NJU6682 can be connected to mpu with the 8/16-bit interface: transferring data twice by 8-bit ,or once by 16-bit. when the 8-bit bus interface is selected, data is transferred only through the d 0 ? d 7 ; the d 8 ? d 15 lines are not used with this interface. then, the 8-bit data transmission is performed twice to complete the data transmission.. the data transmisson is executed through the upper 8 bits(d 15 ? d 8 ) and through the lower 8 bits(d 7 ? d 0 ), respectively. if checking the busy flag(status read) is required, it should be performed after the 2nd data transmission. in this case, the status read is completed only once. when 16-bit bus interface is selected, d 0 ? d 15 lines as 16-bit bus are used once to complete the data transmission. wr terminal d 15 to d 8 d 7 to d 0 terminal ( a ) interface with 8 bit mpu ( 8 bit bus interface mode ) rd terminal d 7 to d 0 status d 15 tod 8 d 7 to d 0 a0 terminal d 15 to d 8 d 7 to d 0 write instruction busy flag check (status read) write display data dummy read d 15 to d 8 d 7 to d 0 read display data
NJU6682 (5-3) serial data input (ps 1 =?l?) the serial interface of the NJU6682 consists of the 16-bit shift register and 4-bit counter. in case the chip is selected (cs=l), the input to d 7 (si) and d 6 (scl) becomes available, and in case that the chip isn't selected, the shift register and the counter are reset to the initial condition. the data input from the terminal(si) is msb first like as the order of d 15 , d 14 , ??? d 0 by a serial interface, it is entered into with rise edge of serial clock(scl). the data converted into parallel data of 16-bit with the rise edge of 16th serial clock and processed. the serial interface of the NJU6682 can be selected out of the 3-wire or 4-wire type according to the ps 0 terminal. in chosen ps 0 terminal to "h", it becomes 4-wire interface and discriminates display data or instructions by a0 input terminal. a0 is read with rise edge of (16 x n)th of serial clock (scl), it is recognized display data by a0=h? and instruction by a0=?l?. a0 input is read in the rise edge of (16 x n)th of serial clock (scl) after chip select and distinguished. however,in case of res=?l? or cs=?h? with trasfered data does not fill 16 bit, attention is necessary because it will processed as there was command input. always, input the data of (16 x n) style. in chosen ps 0 terminal to ?l?,it becomes 3-wire interface and discleminate data after the serial data of 16-bit as the a0 data. note) the scl signal must be careful of the termination reflection by the wiring length and the external noise and confirmation by the actual machine is recommended by it. d 7 to d 0 d 15 to d 8 wr terminal d 15 to d 8 d 15 to d 8 terminal (b) interface with 16 bit mpu (16 bit bus interface mode) rd terminal status d 15 to d 8 a0 terminal d 15 to d 8 write instruction busy flag check (status read) write display data dummy read d 7 to d 0 d 7 to d 0 terminal status d 7 to d 0 d 7 to d 0 read display data
NJU6682 (a) 4-wired serial interface (b) 3-wire serial interface (5-4)display data ram , access of internal register the NJU6682 transfers data to the cpu through the bus holder with the internal data bus. in case of reading out the display data contents in the dd ram, the data which was read in the first data read cycle (= the dummy read ) is memorized in the bus holder. then the data is read out to the system bus from the bus holder in the next data read cycle. also, in case that the mpu writes into dd ram, the data is temporarily stored in the bus holder and is then written into dd ram by the next data write cycle. therefore, the limitation of the access to NJU6682 from mpu side is not access time (t acc ,t ds ) of display data ram and the cycle time becomes dominant. with this, speed-up of the data transfer with the mpu becomes possible. in case of cycle time isn't met, the mpu inserts nop operation only and becomes an equivalent to an execution of wait operation on the sutisfy condition in mpu. when setting an address, the data of the specified address isn't output immediately by the read operation after setting an address, and the data of the specified address is output at the the 2nd data read operation. therefore, the dummy read is always necessary once after the address set and the write cycle. (see fig. 8) the exsample of read modify write operaion is mentioned in (2-1) description of the instruction codesinstruction (q) ? read modify write / end? . ) d 14 d 0 d 1 d 15 18 cs si scl a0 d 14 1 d 15 2 d 12 d 13 3 4 15 16 17 a0=?h?: display data a0=?l?: instruction a0="1":display data a0="0":instruction d 15 d 0 d 1 a 0 18 cs si scl d 14 1 d 15 2 d 12 d 13 4 15 16 17 first transfer data next transfer data first transfer data next transfer data fig 7-1 4-wired serial interface 3 fig 7-2 3-wire serial interface
NJU6682 (5-5) chip select cs is the chip select terminal. in case of cs="l", the interface with mpu is available. in case of cs=?h? (chip is not selected), the terminals of d 0 to d 15 are high impedance and a0, rd, wr, d 7 (si) and d 6 (scl) inputs are ignored. if the serial interface is selected when cs=?h?, the shift register and the counter for the serial interface are reset. however, the reset signal is always input and executed in any conditions of cs. wr address set (n) bus-holder wr mpu internal timing wr data (d 15 ? d 0 ) n n+1 n+2 n+3 n n+1 n+2 n+3 bus-holder wr data read (n+1) dummy read data read (n) data (d 7 ? d 0 ) rd mpu n n+1 n+2 n n+1 n+2 n x address rd wr data (d 7 ? d 0 ) read operation write operation 8bit bus interface 16bit bus interface n(low) n+1(high) n(high) n+1(low) n+2(high) n+2(low) n+3(high) n+3(low) data read (n+1) n n n n+1 address set (n) dummy read data read (n) wr data (d 15 ? d 0 ) rd 8bit bus interface 16bit bus interface n(low) n(high) n(high) n(low) n(high) n(low) n+1(high) n+1(low) fig.8 relation of display read/write and internal timing internal timing
NJU6682 absolute maximum rating parameter symbol ratings unit supply voltage(1) v dd -0.3 to +5.0 v supply voltage(2) v 5 , v out v dd -20.0 to v dd +0.3 v supply voltage(3) v 1 ,v 2 ,v 3 ,v 4 v 5 to v dd +0.3 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -30 to +80 c tcp -55 to +100 strage temperature chip t stg -55 to +125 c (* 1) voltage value is specified as v ss =0 v . (* 2) the relation of v dd v 1 v 2 v 3 v 4 v 5 v out ; v dd >v ss v out must be maintained. in case of inputting external lcd driving voltage , the lcd drive voltage should start supplying to NJU6682 at the mean time of turning on v dd power supply or after turned on v dd . in use of the voltage boost circuit, the condition that the supply voltage: 18.0v v dd -v out is necessary. (* 3) if the lsi are used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the erectric characteristics conditions will cause malfunction and poor reliability. (* 4) decoupling capacitor should be connected between v dd and v ss due to stabilized operation, especially for the voltage converter. v dd v ss v 5 v dd
NJU6682 electrical characteristics (v dd =2.4 to 3.3v, v ss =0v, ta=-30 to +80 c) parameter symbol conditions min typ max unit note operating voltage(1) v dd 2.4 3.3 v 5 v 5 v dd -18.0v v dd -6.0v v 1 ,v 2 v dd -0.5v lcd v dd operating voltage(2) v 3 ,v 4 v lcd =v dd -v5 v5 v dd - 0.5v lcd v 6 high level v ihc1 0.8v dd v dd input voltage low level v ilc1 a0,d 0 -d 15 ,rd,wr,res,cs exclude p/s, sel68,osc1 terminal v ss 0.2v dd v high level v hc11 i oh =-0.5ma 0.8v dd v dd output voltage low level v olc11 d 0 tod 1 terminal i ol = 0.5ma v ss 0.2v dd v input leagage current i li0 all input terminal, d 0 to d 15 terminal in high z -1.0 1.0 a driver on-resistance r on ta=25 c v lcd =15v 2.0 3.0 k ? 7 stand-by current i ddq during power save mode t.b.d t.b.d a 8 i dd01 display v lcd =16v t.b.d t.b.d a 8 operating current in use external power supply i dd02 access f cyc =200khz t.b.d tbd a 9 input terminal capacitance c in ta=25 c 10 pf 10 oscillation frequency f osc vdd= 3.0v, ta=25 c t.b.d khz reset time t r res terminal 1.0 s 11 reset ?l? level pulse width t rw 10 s 12 voltage boost output voltage v out1 7-times boost, v dd =2.5v v dd -17.5v v dd -17.0v v voltage boost on-resistance r tri 7-times boost, v dd =2.5v,cout=4.7 f 3.0 k ? adjustment range of lcd driving voltage v out2 voltage boost operation off v dd - 8.0v v dd - 6.0v v voltage follower v 5 voltage adjustment circuit ?off? v dd - 18.0v v dd - 6.0v v 13 operating current in use internal power supply i out1 display v dd =3v,v lcd =16v, 6-time boost con/sn are open , non-access , display checkerd pattern 300 t.b.d a 14 voltage regulator v reg % v dd =3.0v, ta=25 c t.b.d % *5:although the NJU6682 can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with mpu. *6:the operating voltage when using external power supply. *7:r on is the resistance values in supplying 0.1v voltage-difference beteen power supply terminals (v 1 ,v 2 ,v 3 ,v 4 ) and each output terminals (common/ segment). this is specified within the range of operating voltage(2). *8,9:refers to the current consumption of the ic itself; external power supply is used for the lcd driving. in case of not use internal power supply circuit,meaning current of ic?s. lcd driving power supply are external power supply. *8,9:the value of after driver output on instruction execution. *8:applicable in case of not accessing to the mpu. *9:the operating current when writing a vertical stripe pattern on the tcyc. current consumption during the access is approximately proportional to the access frequency. when not accessed, it consumpts only i dd01 . *10:apply to a0,d 0 -d 15 ,rd,wr,cs,res,sel68,ps 0 ,ps 1 terminals *11:t r ( reset time ) refers to the reset completion time of the internal circuits from the rise edge of the res signal. *12:apply minimum pulse width of the res signal. to reset, the "l" pulse over t rw shall be input. . *13:the voltage adjustment circuit controls v 5 within the range of the voltage follower operating voltage.
NJU6682 *14:each operating current shall be defined as being measured in the following condition. power supply set instruction operating condition symbol dc vr vf internal oscillator voltage booster voltage adjustment v/f circuit external voltage supply (input terminal) i dd1 1 1 1 validity validity (6-time boost) validity validity unuse ? lcd output terminals are open (no connection). ? display on,display checkered pattern,no access from mpu ? set v lcd =16v ? set to r 1 +r 2 +r 3 =2m ? measurement block diagram :i out1 a + vdd v5 vr r1 r2 r2 vout c1+ c1- c2- c2+ + + + c3- c4- vss NJU6682 + c5- c6-
NJU6682 bus timing characteristics ? read/write operation sequence(80 type mpu) (v dd =2.4v to 3.3v, ta=-30 to 80 c) parameter signal symbol measurement condition min typ max unit address hold time t ah8 0 address set up time a0,cs t aw8 0 system cycle time (write) t cyc8 (w) 160 system cycle time (read) t cyc8 (r) 360 control pulse width (wr) t ccl (w) 50 control pulse width (rd) wr rd t ccl (r) 250 control ?h? pulse width wr,rd t cch 110 data set up time t ds8 30 data hold time t dh8 5 rdaccess time t acc8 240 output disable time d 0 to d 7 d 8 to d 15 t oh8 cl=100pf 0 50 rise time / falltime cs,wr,rd tr, tf 15 ns *15 all timing based on 20% and 80% of v dd voltage level. t cyc8 t f t r t aw 8 t ah8 t ccl t cch t ds8 t dh8 t acc8 t oh8 d 0 ? d 8 d 0 ? d 15 (16 bit bus mode) (write) a0 wr,rd (cs) d 0 ? d 8 d 0 ? d 15 (16 bit bus mode) (read)
NJU6682 ? system bus sequence (read / write) (68-type mpu) (v dd =2.4v to 3.3v, ta=-30 to 80 c) parameter signal symbol measurement condition min typ max unit address hold time t ah6 0 address set up time t aw6 0 system cycle time (write) t cyc6 (w) 160 system cycle time (read ) a0,cs r/w t cyc6 (r) 360 read 250 enable ?h? pulse width write t ewh 50 enable ?l? pilsewidth (read/write) e t ewl 110 data set up time t ds6 30 data hold time t dh6 5 access time t acc6 240 output disable time d 0 to d 7 , d 8 to d 15 t oh6 cl=100pf 0 50 rise time / fall time tr, tf e 15 ns *16 all timing are based on 20% and 80% of v dd voltage level. *17 t cyc6 shows the cycle of the e signal in active cs. e t cyc6 t ewh t aw 6 t ah6 t ds6 t dh6 t acc6 t oh6 t r t f t ewl r/w a0,cs d 0 ? d 7 , d 8 ? d 15 (16 bit bus mode) (write) d 0 ? d 7 , d 8 ? d 15 (16 bit bus mode) (read)
NJU6682 ? serial interfave (vdd=2.4v to 3.3v, ta=-30 to 80 c) parameter signal symbol measurement condition min typ max unit instruction input t scyc1 60 serial clock cycle instruction time* 19) t scyc2 200 scl"h" pulse width t shw 30 scl"l" pilse width scl t slw 30 address set up time t sas 15 address hold time a0 t sah 15 data set up time t sds 15 data hold time si t sdh 15 t css 30 cs-scltime cs t csh 30 rise time / fall time scl tf, tr 15 ns *18 all timing are based on 20% and 80% of v dd voltage level. *19 when inputting an instruction continuously, keep 200ns as the cycle of scl between the instructions as follows scl 16 th clock(4-wire) scl 17 th clock(3-wire) scl 1 st clock scl t scyc2 (200ns) instruction (n th) scl?l?pulse width instruction (n+1 th) (instruction time) cs a0 scl si t css t csh t sas t sah t scyc1 t slw t shw t f t r t sdh t sds
NJU6682 lcd driving wave form (black & white mode) v 5 v 4 v 3 v 2 v 1 v dd -v 1 -v 2 -v 3 -v 4 -v 5 c5 c4 c3 c2 c1 c0 c15 c7 c6 c13 c12 c11 c10 c9 c8 c14 s3 s4 s2 s1 s0 fr c1 c0-s1 c0-s0 s1 s0 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 c0 c2 v dd v 1 v 2 v 3 v 4 v 5 v dd v ss v 4 v 3 v 2 v 1 v dd -v 1 -v 2 -v 3 -v 4 -v 5 v 5
NJU6682 application circuit mpu interface example NJU6682 can direct connection with 80 type mpu and 68 type mpu. moreover, with to use a serial interface, it is possible to control by the signal line with the more small being. *sel68 terminal should be connect v dd or v ss 80 type mpu cpu a0 sel68 ps1 decoder NJU6682 ps0 v cc a1 ? a15 iorq d 0 ? d 7 d 8 ? d 15 rd wr res gnd a 0 v dd cs d 0 ? d 7 d 8 ? d 15 rd wr res v ss reset v dd 68 type mpu cpu a0 sel68 ps1 decoder NJU6682 ps0 v cc a1 ? a15 vma d 0 ? d 7 d 8 ? d 15 e r/w res gnd a 0 v dd cs d 0 ? d 7 d 8 ? d 15 e r/w res v ss reset v dd v dd serial interface (4-wire) cpu a0 sel68 ps1 decoder NJU6682 ps0 v cc a1 ? a7 res gnd a 0 v dd cs d7 ( si ) d6(scl) res v ss reset v dd v dd port 1 port 2
NJU6682 memo [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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